The present invention relates to a PWM (Pulse Width Modulation) signal outputting circuit and a method of controlling an output of a PMW signal. More specifically, the present invention relates to a PWM signal outputting circuit and a method of controlling an output of a PMW signal capable of efficiently adding a dead time (a period of time during which each PMW signal is not turned on simultaneously) to each PWM signal having a cyclic period and a duty arbitrarily defined thereto.
In general, a PWM (Pulse Width Modulation) signal has been used for controlling an IGBT (Insulated Gate Bipolar Transistor) and the like disposed for controlling an inverter circuit of an IH (Induction Heating) cooking device and a non-power outage power source device.
For example, an inverter circuit disposed in the IT cooking device is formed of two switching elements, so that the two switching elements are controlled to turn on and off through the PWM signal. In the inverter circuit with such a configuration, when the two switching elements are turned on simultaneously, a through current may flows, thereby causing damage in an inverter control circuit.
In order to prevent the inverter control circuit from being damaged, Patent References 1 to 3 have disclosed technologies, in which an inverter control micro-computer is configured to output a PWM signal with a dead time.    Patent Reference 1: Japanese Patent Publication No. 2004-187492    Patent Reference 2: Japanese Patent Publication No. 2004-357450    Patent Reference 3: Japanese Patent Publication No. 2007-202329
For example, according to Patent Reference 1, a semiconductor device is configured to generate a mutually compensated PWM signal for controlling an inverter circuit. The semiconductor device has a configuration that is configured to make it possible to easily and flexibly add a period of time during which each PMW signal is not turned on simultaneously (the dead time) relative to each of the two PWM signals.
More specifically, the semiconductor device disclosed in Patent Reference 1 includes a first mutually compensated PWM signal generation unit for generating a first PWM signal and a second PWM signal as an inverted signal of the first PWM signal, and a dead time adding unit for adding a first dead time when the first PWM signal is raised and a second dead time when the second PWM signal is raised. Further, the dead time adding unit is configured to be capable of setting the first dead time and the second dead time individually.
Further, in the semiconductor device disclosed in Patent Reference 1, the dead time adding unit includes a dead timer, a first dead time setting register, and a second dead time setting register. Accordingly, the dead time adding unit is configured to be capable of adding a period of time that a value of the dead timer reaches a setting value of the first dead time setting register as the first dead time when the first PMW signal is raised. Further, the dead time adding unit is configured to be capable of adding a period of time that the value of the dead timer reaches a setting value of the second dead time setting register as the second dead time when the second PMW signal is raised.
With the configuration of the dead time adding unit described above, it is possible to set the different dead times relative to the PWM signal and the inverted signal thereof. Accordingly, it is not necessary to change and set the optimal value of the dead time in the semiconductor device. At the same time, it is possible to individually set the optimal dead time, thereby making it possible to accurately control the inverter circuit without increasing power consumption.
In the semiconductor device disclosed in Patent Reference 1, however, it is difficult to solve the following problems.
For example, the semiconductor device includes an IC (Integrated Circuit) for outputting the PWM signal. However, the IC is not necessarily configured to output the mutually compensated signals (the signals with the inverted phases). The IC is desired to have a configuration capable of controlling two phases regardless of outputting the mutually compensated signals or totally different signals. To this end, it is necessary to configure the IC to be able to arbitrarily control a cyclic period and a duty.
A conventional PWM signal outputting circuit will be explained next with reference to FIGS. 1 and 2. The conventional PWM signal outputting circuit has a configuration capable of arbitrarily controlling the cyclic period and the duty relative to each of a plurality of PWM signals.
FIG. 1 is a block diagram showing the configuration of the conventional PWM signal outputting circuit capable of arbitrarily controlling the cyclic period and the duty. FIG. 2 is a timing chart showing an example of an operation of the conventional PWM signal outputting circuit.
As shown in FIG. 1, the conventional PWM signal outputting circuit is formed of, for example, a semiconductor device such as a micro-computer and the like. The conventional PWM signal outputting circuit includes a counter 11; a channel 1 cyclic period setting register 12; a channel 1 duty setting register 13; a channel 2 cyclic period setting register 14; a channel 2 duty setting register 15; a first comparing unit 16a; a second comparing unit 16b; a third comparing unit 16c; a fourth comparing unit 16d; a channel 1 output control circuit 17; and a channel 2 output control circuit 18.
In the conventional PWM signal outputting circuit, the counter 11 is configured to operate synchronizing with a clock output from, for example, a timer and the like disposed in the micro-computer, so that the counter 11 counts the number of the clocks and outputs the number as a counter value.
In the conventional PWM signal outputting circuit, the channel 1 cyclic period setting register 12, the channel 1 duty setting register 13, the first comparing unit 16a, the second comparing unit 16b and the channel 1 output control circuit 17 constitute a first PWM signal generating unit for outputting a first PWM signal (PWM1). Similarly, the channel 2 cyclic period setting register 14, the channel 2 duty setting register 15, the third comparing unit 16c, the fourth comparing unit 16d and the channel 2 output control circuit 18 constitute a second PWM signal generating unit for outputting a second PWM signal (PWM2).
In the conventional PWM signal outputting circuit having the configurations described above, the first PWM signal generating unit and the second PWM signal generating unit are configured to generate and output the PWM signal with the duty value corresponding to the values set in the channel 1 cyclic period setting register 12, the channel 1 duty setting register 13, the channel 2 cyclic period setting register 14, and the channel 2 duty setting register 15, respectively, according to the counter value output from the counter 11.
In the conventional PWM signal outputting circuit, the first comparing unit 16a has a function as a reset circuit for resetting the counting operation of the counter 11 when the counter value output from the counter 11 reaches a specific value defined in advance.
In the conventional PWM signal outputting circuit, the first PWM signal generating unit and the second PWM signal generating unit are configured to store the values set in the channel 1 duty setting register 13 and the channel 2 duty setting register 15 as a start setting value, respectively. Further, the second comparing unit 16b and the fourth comparing unit 16d are configured to compare the counter value output from the counter 11 with the start setting values stored in the channel 1 duty setting register 13 and the channel 2 duty setting register 15, respectively. Further, the first PWM signal generating unit and the second PWM signal generating unit are configured to generate and output a start signal when the counter value matches to the start setting values.
Accordingly, when the second comparing unit 16b and the fourth comparing unit 16d output the start signals, the channel 1 output control circuit 17 and the channel 2 output control circuit 18 of the first PWM signal generating unit and the second PWM signal generating unit generate and output the first PWM signal (PWM1) and the second PWM signal (PWM2), respectively.
In the conventional PWM signal outputting circuit, the first PWM signal generating unit and the second PWM signal generating unit are configured to store the values set in the channel 1 cyclic period setting register 12 and the channel 2 cyclic period setting register 14 as a termination setting value, respectively. Further, the first comparing unit 16a and the third comparing unit 16c are configured to compare the counter value output from the counter 11 with the termination setting values stored in the channel 1 cyclic period setting register 12 and the channel 2 cyclic period setting register 14, respectively. Further, the first PWM signal generating unit and the second PWM signal generating unit are configured to generate and output a termination signal when the counter value matches to the termination setting values.
Accordingly, when the first comparing unit 16a and the third comparing unit 16c output the termination signals, the channel 1 output control circuit 17 and the channel 2 output control circuit 18 of the first PWM signal generating unit and the second PWM signal generating unit stop generating and outputting the first PWM signal (PWM1) and the second PWM signal (PWM2), respectively.
The operation of the first PWM signal generating unit and the second PWM signal generating unit will be explained next with reference to FIG. 2.
In the operation shown in FIG. 2, the termination setting value “7” is set in the channel 1 cyclic period setting register 12; the start setting value “2” is set in the channel 1 duty setting register 13; the termination setting value “4” is set in the channel 2 cyclic period setting register 14; and the start setting value “1” is set in the channel 2 duty setting register 15, respectively. With the setting values set as described above, the counter 11 operates synchronizing with the clock. When the counter value of the counter 11 matches to the start setting value “2” set in the channel 1 duty setting register 13, the second comparing unit 16b generates and outputs the start signal to the channel 1 output control circuit 17.
Accordingly, the PWM1 output from the channel 1 output control circuit 17 is changed from “L” (low) to “H” (high). Afterward, when the counter value of the counter 11 matches to the termination setting value “7” set in the channel 1 cyclic period setting register 12, the first comparing unit 16a generates and outputs the termination signal to the channel 1 output control circuit 17. Accordingly, the PWM1 output from the channel 1 output control circuit 17 is changed from “H” (high) to “L” (low). Further, the value of the counter 11 is cleared.
Further, when the counter value of the counter 11 matches to the start setting value “1” set in the channel 2 duty setting register 15, the fourth comparing unit 16d generates and outputs the start signal to the channel 2 output control circuit 18. Accordingly, the PWM2 output from the channel 2 output control circuit 18 is changed from “L” (low) to “H” (high). Afterward, when the counter value of the counter 11 matches to the termination setting value “4” set in the channel 2 cyclic period setting register 14, the third comparing unit 16c generates and outputs the termination signal to the channel 2 output control circuit 18. Accordingly, the PWM2 output from the channel 2 output control circuit 18 is changed from “H” (high) to “L” (low). Further, the PWM2 output is maintained at “H” (high) until the counter value of the counter 11 matches to the termination setting value “7” set in the channel 1 cyclic period setting register 12, that is, the value of the counter 11 is cleared.
Through the process described above, in the conventional PWM signal outputting circuit having the configuration shown in FIG. 1, it is possible to arbitrarily set the cyclic period and the duty with respect to the two channels.
As described above, in the first PWM signal generating unit and the second PWM signal generating unit, it is possible to arbitrarily set the start setting values and the termination setting values. As shown in FIG. 2, however, when the start setting values and the termination setting values are set, there is a period of time when both the first PWM signal PWM1 and the second PWM signal PWM2 output from the first PWM signal generating unit and the second PWM signal generating unit become “H”.
In the conventional PWM signal outputting circuit, when both the first PWM signal PWM1 and the second PWM signal PWM2 become “H”, and the first PWM signal generating unit and the second PWM signal generating unit are turned on (ON) during the period of time when both the first PWM signal PWM1 and the second PWM signal PWM2 become “H”, there is a period of time when the two channels are simultaneously turned on. For example, when both the first PWM signal PWM1 and the second PWM signal PWM2 are used for controlling the IGBT and the like, a component of the IGBT may be damaged.
As described above, in the conventional PWM signal outputting circuit having the configuration shown in FIG. 1, it is possible to arbitrarily set the cyclic period and the duty with respect to the two channels. However, when the conventional PWM signal outputting circuit is used for controlling the IGBT and the like, the two channels are simultaneously turned on accidentally due to wrong setting.
In view of the problems described above, an object of the present invention is to provide a PWM signal outputting circuit and a method of controlling a PWM signal output capable of solving the problems of the conventional PWM signal outputting circuit. In the present invention, it is possible to set a plurality of PWM signals with a higher degree of flexibility. Further, it is possible to perform a proper operation even when each of the PWM signals is used in a mutually compensating manner.
Further objects and advantages of the present invention will be apparent from the following description of the present invention.